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  3. Very Large Scale Integration (VLSI) Systems
  4. Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages
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Category: Very Large Scale Integration (VLSI) Systems
By MTech Projects
MTech Projects
15.May
Hits: 69

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

PROJECT TITLE :

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

ABSTRACT:

In this transient, a methodology for compressing the messages between check nodes and variable nodes is proposed. This technique is named compressed nonbinary message passing (CNBMP). CNBMP reduces the amount of messages exchanged between one check node and therefore the connected variable nodes from dc x q to five × q, and its application includes a high impact on the performance of the decoder: the storage and routing areas are reduced and also the throughput is increased. Unlike different methods, CNBMP does not introduce any approximation or modification in the information and therefore the processed operations are precisely the identical as those of the first decoders; hence, no performance degradation is introduced. To demonstrate its benefits, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were conjointly reduced from dc × q to five × q. This design was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an space of 10.sixty seven mm2, that is 3.nine additional economical than the best solution found within the literature.

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