PROJECT TITLE :

A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links

ABSTRACT:

A zero.0015-mm2 1.twenty eight-mW single-branch analog equalizer is demonstrated in 65-nm CMOS for 10-Gb/s input/output links. Instead of using passive inductors that are untunable and unscalable with technologies, gain compensation here is optimized via a tunable and currentreusable active inductor (AI). This AI incorporates a positive-feedback impedance converter with only two MOSFETs and one MOS varactor. Along with the use of: 1) negative Miller capacitors to optimize the pole-zero composition and a pair of) tunable resistive supply degeneration to regulate the low-frequency losses, the analog equalizer recovers an eye-opening rate of minimally 30p.c up to ten Gb/s over a pair of 60-cm FR4 microtrip traces. The info Pk-to-Pk jitter is <;24 ps, and also the RMS jitter is <;4 ps, over a range of pseudorandom bit sequence patterns (twenty seven-1, 215-one, and 231-one).