PROJECT TITLE :

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

ABSTRACT:

A system clock with a 50p.c duty cycle is demanded in high-speed information Communication applications, such as double data rate recollections and double sampling analog-to-digital converters. During this paper, a wide-vary low-value all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to scale back the required length of the delay line to [*fr1] of the input clock period. Thus, it will extend the operating frequency toward a lower frequency with little space cost as compared with the traditional style. The proposed design is implemented during a commonplace performance ninety-nm CMOS method, and therefore the active space is a hundred and seventy × one hundred seventy μm2. The input frequency of the proposed ADDCC ranges from seventy five to 734 MHz, and also the input duty-cycle ranges from ninepercent to 86%. The measured output duty-cycle error is but one.78percent. The proposed ADDCC consumes 4.59 mW at 734 MHz and zero.nine mW at seventy five MHz with a 1.zero-V power offer.