PROJECT TITLE :

Coupling Mitigation in 3-D Multiple-Stacked Devices

ABSTRACT:

A 3-d multiple-stacked IC has been proposed to support energy potency for knowledge center operations as dynamic RAM (DRAM) scaling improves annually. three-D multiple-stacked IC is a single package containing multiple dies, stacked along, using through-silicon via (TSV) technology. Despite the advantages of 3-D design, fault incidence rate will increase with feature-size reduction of logic devices, which gets worse for 3-D stacked designs. TSV coupling is one in every of the most reliability issues for 3D multiple-stacked IC information TSVs. It's giant disruptive effects on signal integrity and transmission delay. During this paper, we tend to initial characterize the inductance parasitics in contemporary TSVs, and then we analyze and gift a classification for inductive coupling cases. Next, we tend to devise a coding algorithm to mitigate the TSV-to-TSV inductive coupling. The coding methodology controls the current flow direction in TSVs by adjusting the data bit streams at run time to minimize the inductive coupling effects. After performing formal analyses on the potency scalability of devised algorithm, an enhanced approach supporting larger bus sizes is proposed. Our experimental results show that the proposed coding algorithm yields vital improvements, whereas its hardware-implemented encoder leads to tangible latency, power consumption, and area.