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IEEE ROOT Projects at MTech Projects feature the latest project topics with Abstract, Source Code, Thesis, Report, Documentation, Research Paper Writing, Presentation ppt, Video demo, and Expert guidance for BTech, MTech, BE, ME, MS and PhD students. We support engineering students and researchers across Hyderabad, Bengaluru, Chennai, Mumbai, Delhi, Pune, Kolkata, Ahmedabad, Kochi and other major cities in India, USA, UK.

Latest ROOT IEEE Project Titles [2026]

S.No Project Title Abstract
281 NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices - 2016 Abstract
282 A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies - 2016 Abstract
283 Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016 Abstract
284 A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes - 2016 Abstract
285 A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing - 2016 Abstract
286 Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems - 2016 Abstract
287 Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division - 2016 Abstract
288 Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 Abstract
289 Trigger-Centric Loop Mapping on CGRAs - 2016 Abstract
290 PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash - 2016 Abstract
291 Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016 Abstract
292 A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic - 2016 Abstract
293 An Efficient Decoder Architecture for Non-binary LDPC Codes with Extended Min-Sum Algorithm - 2016 Abstract
294 An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding - 2016 Abstract
295 An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016 Abstract
296 CWFP: Novel Collective Write back and Fill Policy for LastLevel DRAM Cache - 2016 Abstract
297 High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 Abstract
298 Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016 Abstract
299 A Multimode Area-Efficient SCL Polar Decoder - 2016 Abstract
300 Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 Abstract

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