PROJECT TITLE :

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic - 2016

ABSTRACT:

This paper proposes a high-throughput energy-economical Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at comparatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to supply a favorable tradeoff between throughput and energy potency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low-complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybrid-logic decoders with respect to purely synchronous architectures.