PROJECT TITLE :

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add - 2018

ABSTRACT:

The need for power potency is driving a rethink of style selections in processor architectures. Whereas vector processors succeeded in the high-performance market within the past, they have a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating may be a well-known technique to cut back switching power in synchronous styles, there are unexplored opportunities for its application to vector processors, particularly when considering active operating mode. During this analysis, we have a tendency to comprehensively establish, propose, and evaluate the most appropriate clock-gating techniques for vector FMA units (VFUs). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using each artificial and “real-world” application-primarily based benchmarking. Using vector masking and vector multilane-aware clock gating, we tend to report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we have a tendency to observe that vector instruction-based mostly clock-gating techniques achieve power savings for all vector FP instructions. Finally, when evaluating all techniques along, using “real-world” benchmarking, the power reductions are up to eightyp.c. Additionally, in accordance with processor style trends, we have a tendency to perform this analysis in an exceedingly fully parameterizable and automated fashion.