PROJECT TITLE :

On Efficient Retiming of Fixed-Point Circuits - 2016

ABSTRACT:

Retiming of digital circuits is conventionally based mostly on the estimates of propagation delays across completely different ways in the information-flow graphs (DFGs) obtained by discrete part timing model, which implicitly assumes that operation of a node will begin solely when the completion of the operation(s) of its preceding node(s) to obey the information dependence demand. Such a discrete element timing model terribly typically gives abundant higher estimates of the propagation delays than the actuals notably when the computations within the DFG nodes correspond to fastened-point arithmetic operations like additions and multiplications. On the other hand, very often it's imperative to house the DFGs of such higher granularity at the design-level abstraction of digital system design for mapping an algorithm to the specified architecture, where the overestimation of propagation delay leads to unwanted pipelining and undesirable increase in pipeline overheads. During this paper, we propose the connected part timing model to get adequately precise estimates of propagation delays across completely different combinational methods in a very DFG simply, for economical cutset-retiming so as to reduce the vital path substantially without significant increase in register-complexity and latency. Apart from that, we tend to propose novel node-splitting and node-merging techniques that may be utilized in combination with the present retiming ways to realize reduction of important path to a fraction that of the first DFG with a tiny increase in overall register complexity.