Key Reconciliation Protocols for Error Correction of Silicon PUF Responses - 2017

Power Optimization of Communication System Using Clock Gating Technique - 2015

Revisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI - 2015

Design and simulation of CRC encoder and decoder using VHDL - 2018

Multifunction Residue Architectures for Cryptography

Approximate Quaternary Addition with the Fast Carry Chains of FPGAs - 2018

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016

An Efficient Decoder Architecture for Non-binary LDPC Codes with Extended Min-Sum Algorithm - 2016