PROJECT TITLE:

Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics - 2015

ABSTRACT:

This project briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we have a tendency to have designed multiplier based on the sutra. Vedic Mathematics is the traditional system of mathematics that includes a unique technique of calculations based mostly on sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. During this era of digitalization, it's required to increase the speed of the digital circuits while reducing the on chip space and memory consumption. In numerous applications of Digital Signal Processing, multiplication is one in all the key element. Vedic technique eliminates the unwanted multiplication steps thus reducing the propagation delay in processor and hence reducing the hardware complexity in terms of area and memory requirement. We have a tendency to implement the fundamental building block: sixteen × sixteen Vedic multiplier based on Urdhva-Tiryagbhyam Sutra. This Vedic multiplier is coded in VHDL and synthesized and simulated by using Xilinx ISE 10.one. Further the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory.