PROJECT TITLE:

A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links - 2015

ABSTRACT:

A 0.0015-mm2 1.twenty eight-mW single-branch analog equalizer is demonstrated in 65-nm CMOS for 10-Gb/s input/output links. Instead of using passive inductors that are untunable and unscalable with technologies, gain compensation here is optimized via a tunable and currentreusable active inductor (AI). This AI incorporates a positive-feedback impedance converter with solely two MOSFETs and one MOS varactor. Together with the employment of: one) negative Miller capacitors to optimize the pole-zero composition and a couple of) tunable resistive source degeneration to regulate the low-frequency losses, the analog equalizer recovers a watch-opening rate of minimally thirty% up to ten Gb/s over a pair of sixty-cm FR4 microtrip traces. The info Pk-to-Pk jitter is <;24 ps, and the RMS jitter is <;four ps, over a range of pseudorandom bit sequence patterns (twenty seven-1, 215-1, and 231-1).