PROJECT TITLE :

Cascaded multilevel inverter using series connection of novel capacitor-based unitswith minimum switch count - 2016

ABSTRACT:

This paper presents a new family of cascaded multilevel inverters (CMLIs) that will generate a considerable number of output voltage levels with minimum number of needed accompanying switching devices. Conceptually, every stage of proposed CMLI consists of using a novel capacitor-primarily based unit including two floating capacitors, one embedded dc voltage source and 3 power switches. In this case, the balanced voltage of integrated capacitors will be precisely provided as self-voltage balancing without using any auxiliary circuits, close loop systems and intricate modulation techniques. As well, to succeed in completely different variety of output voltage levels, four different algorithms regarding the symmetrical, binary asymmetrical, trinary asymmetrical and also hybrid patterns for determining the magnitude of isolated dc voltage sources are presented. Hereby, proposed hybrid structure is capable of working underneath mixed switching frequency while not aiming the traditional full H-Bridge cell. Therefore, a high quality of output waveforms with reduced switching devices along with power loss dissipation will be alternatively achieved. To ensure the validity of proposed CMLI, a complete comparison with many recently presented topologies besides several simulation and experimental results based on trinary asymmetrical and hybrid evolved structures will be also given.