PROJECT TITLE :

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

ABSTRACT:

We tend to present an economical combined single-path delay commutator-feedback (SDC-SDF) radix-a pair of pipelined quick Fourier transform design, which includes log2 N - 1 SDC stages, and one SDF stage. The SDC processing engine is proposed to attain 100% hardware resource utilization by sharing the common arithmetic resource within the time-multiplexed approach, together with both adders and multipliers. So, the specified number of advanced multipliers is reduced to log4 N - zero.5, compared with log2 N - 1 for the other radix-two SDC/SDF architectures. In addition, the proposed design requires roughly minimum range of complex adders log2 N + 1 and complex delay memory 2N + 1.5log2 N - one.5.